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CY7C2245KV18 36-mbit qdr ? ii+ sram four-word burst architecture (2.0 cycle read latency) with odt cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-87885 re v. *d revised january 4, 2018 36-mbit qdr ? ii+ sram four-word burst architecture (2.5 cycle read latency) with odt features separate independent r ead and write data ports ? supports concurrent transactions 450 mhz clock for high bandwidth four-word burst for reduc ing address bus frequency double data rate (ddr) interfaces on both read and write ports (data transferred at 900 mhz) at 450 mhz available in 2.0 clock cycle latency two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high speed systems data valid pin (qvld) to indi cate valid data on the output on-die terminati on (odt) feature ? supported for d [x:0] , bws [x:0] , and k/k inputs single multiplexed address input bus latches address inputs for read and write ports separate port selects for depth expansion synchronous internally self-timed writes qdr ? ii+ operates with 2.0 cycl e read latency when doff is asserted high operates similar to qdr i device with 1 cycle read latency when doff is asserted low available in 36 configurations full data coherency, providing most current data core v dd = 1.8 v 0.1 v; i/o v ddq = 1.4 v to v dd [1] ? supports both 1.5 v and 1.8 v i/o supply hstl inputs and variable drive hstl output buffers available in 165-ball fbga p ackage (13 15 1.4 mm) offered in pb-free packages jtag 1149.1 compatible test access port phase-locked loop (pll) f or accurate data placement configurations with read cycle latency of 2.0 cycles: CY7C2245KV18 C 1m 36 functional description the CY7C2245KV18 is 1.8 v synchronous pipelined sram, equipped with qdr ii+ architecture. similar to qdr ii architecture, qdr ii+ architecture consists of two separate por ts: the read port and the write port to access the memory array. th e read port has dedicated data outputs to support read operations and the write port has dedicat ed data inputs to support write operations. qdr ii+ architectu re has separate data inputs and data outputs to completely eliminate the need to turn-around the data bus that exists with common i/o devices. each port is accessed through a common address bus. addresses for read and write addresses are latche d on alternate rising edges of th e input (k) clock. accesses to the qdr ii+ read and write ports a re completely independent of one another. to maximize data throughput, both read and write ports are equipped with ddr interfaces. each address location is associated with four 36-bi t words (CY7C2245KV18) that burst s equentially into or out of the device. because data is transferred into and out of the device on every rising edge of both input clocks (k and k ), memory bandwidth is maximized while simplifying system design by eliminating bus turn-arounds. these devices have an on-die te rmination feature supported for d [x:0] , bws [x:0] , and k/k inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing. depth expansion is accomplished with port selects, which enables each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the k or k input clocks. writes are conducted with on-chip synchron ous self-timed write circuitry. for a complete list of re lated documentation, click here . selection guide description 450 mhz unit maximum operating frequency 450 mhz maximum operating current 36 1020 ma note 1. the cypress qdr ii+ devices su rpass the qdr consortium specif ication and can support v ddq = 1.4 v to v dd .
CY7C2245KV18 document number: 001-87885 rev. *d page 2 of 28 logic block diagra m C CY7C2245KV18 256k x 36 array clk a (17:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 72 18 144 36 bws [3:0] v ref write add. decode write reg 72 a (17:0) 18 256k x 36 array 256k x 36 array 256k x 36 array 36 cq cq doff q [35:0] qvld 36 36 36 write reg write reg write reg 36
CY7C2245KV18 document number: 001-87885 rev. *d page 3 of 28 contents pin configurations ............................................ ............... 4 pin definitions ............................................... ................... 5 functional overview ........................................... ............. 6 read operations ............................................... .......... 6 write operations .............................................. ........... 7 byte write operati ons ......................................... ........ 7 concurrent transactions ....................................... ...... 7 depth expansion ............................................... .......... 7 programmable impedance ..... .............. ........... .......... .. 7 echo clocks ....... ............ ........... ........... .......... ............. 7 valid data indicator (qvld) ................................... ..... 7 on-die termination (odt) ...................................... .... 7 pll ........................................................... ................... 7 application example ........................................... ............. 8 truth table ................................................... ..................... 9 write cycle descriptions ...................................... ......... 10 ieee 1149.1 serial boundary sc an (jtag) ...... ............ 11 disabling the jtag feature .................................... .. 11 test access port .............................................. ......... 11 performing a tap reset ..... ................................... ... 11 tap registers ................................................. .......... 11 tap instruction set ........................................... ........ 11 tap controller state diagram .................................. ..... 13 tap controller block diagram .................................. .... 14 tap electrical characteristics ................................ ...... 14 tap ac switching characteristics .............................. .15 tap timing and test conditions ................................ .. 16 identification register definitions ........................... ..... 17 scan register sizes ........................................... ............ 17 instruction codes ............................................. .............. 17 boundary scan order ........................................... ......... 18 power up sequence in qdr ii+ sram ......................... 19 power up sequence ............................................. .... 19 pll constraints ............................................... .......... 19 maximum ratings ............................................... ............ 20 operating range ............................................... .............. 20 neutron soft error immunity ................................... ...... 20 electrical characteristics .................................... ........... 20 dc electrical characteristi cs ................................. .... 20 ac electrical characteristics ................................. .... 21 capacitance ................................................... ................. 21 thermal resistance ............................................ ............ 21 ac test loads and waveforms ................................... .. 21 switching characteristics ..................................... ......... 22 switching waveforms ........................................... ......... 23 read/write/deselect sequence ............. ........... ........ 23 ordering information .......................................... ............ 24 ordering code definitions ..................................... .... 24 package diagram ............................................... ............. 25 acronyms ...................................................... .................. 26 document conventions .......................................... ....... 26 units of measure .............................................. ......... 26 document history page ......................................... ........ 27 sales, solutions, and legal information ...................... 2 8 worldwide sales and design s upport ......... .............. 28 products ...................................................... .............. 28 psoc? solutions ............................................... ....... 28 cypress developer community . ................................ 28 technical support ........... .................................. ........ 28
CY7C2245KV18 document number: 001-87885 rev. *d page 4 of 28 pin configurations the pin configuration for CY7C2245KV18 follow. [2] figure 1. 165-ball fbga (13 15 1.4 mm) pinout CY7C2245KV18 (1m 36) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/288m nc/72m wps bws 2 k bws 1 rps a nc/144m cq b q27 q18 d18 a bws 3 kbws 0 ad17q17q8 c d27 q28 d19 v ss ancav ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss aaav ss q10 d9 d1 p q35 d35 q26 a a qvld a a q9 d0 q0 r tdotckaaaodtaaatmstdi note 2. nc/72m, nc/144m, and nc/288m are not connected to the die and can be tied to any voltage level.
CY7C2245KV18 document number: 001-87885 rev. *d page 5 of 28 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals . sampled on the rising edge of k and k clocks when valid write operations are active. CY7C2245KV18 ? d [35:0] wps input- synchronous write port select ? active low . sampled on the rising edge of the k clock. when asserted acti ve, a write operation is initiated. de asserting deselects the write p ort. deselecting the write port ignores d [x:0] . bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2 and 3 ? active low . sampled on the rising edge of the k and k clocks when write operations are active. us ed to select which byte is writt en into the device during the current portion of the write operations. bytes not written remain unaltered. CY7C2245KV18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27]. all the byte write selects are sampled on the same edge as the data. deselecting a byte write select ignores the corresponding byte of data and it is not written in to the device . a input- synchronous address inputs . sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write op erations. internally, the device is organized as 1m 36 (4 arrays each of 256k 36) for cy7c2245k v18. therefore, only 18 address inputs for CY7C2245KV18. these inputs are ignored when the appr opriate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data when the read operati on is active. valid data is driven out on the rising edge of the k and k clocks during read operations. on deselecting the read port, q [x:0] are automatically tri-stated. CY7C2245KV18 ? q [35:0] rps input- synchronous read port select ? active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting deselects the read por t. when deselected, the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the k clock. each read access consists of a burst of four sequential transfers. qvld valid output indicator valid output indicator . the q valid indicates valid output data. qvld is edge aligned with cq and cq . odt [3] on-die termination input pin on-die termination input . this pin is used for on-die termination of the input signals. odt range selection is made during power up initialization. a low on this pin selects a low range that follows rq/3.33 for 175 ?? < rq < 350 ?? (where rq is the resistor tied to zq pin) ?? a high on this pin selects a high range that follows rq/1.66 for 175 ?? < rq < 250 ?? (where rq is the resistor tied to zq pin). when left floating, a high range termination value is selected by de fault. k input clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] . all accesses are initiat ed on the rising edge of k. k input clock negative input clock input . k is used to capture synchronous inputs being presented to the d evice and to drive out data through q [x:0] . cq echo clock synchronous echo clock outputs . this is a free running clock a nd is synchronized to the input clock (k) of the qdr ii+. the timings for the echo clocks are shown i n the switching characteristics on page 22 . cq echo clock synchronous echo clock outputs . this is a free running clock a nd is synchronized to the input clock (k ) of the qdr ii+.the timings f or the echo clocks are shown in t he switching characteristics on page 22 . zq input output impedance matching input . this input is used to tune th e device outputs to the system d ata bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 rq, where rq is a resistor connected between zq and ground. a lternatively, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connecte d directly to gnd or left unconnected. note 3. on-die termination (odt) feature is supported for d [x:0] , bws [x:0] , and k/k inputs.
CY7C2245KV18 document number: 001-87885 rev. *d page 6 of 28 functional overview the CY7C2245KV18 is synchronous pipelined burst sram equipped with a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows int o the sram through the write po rt and flows out through the read port. these devices multiplex th e address inputs to minimize the number of address pins required. by having separate read and write ports, the qdr ii+ completely eliminates the need to turn-around the data bus and avoids an y possible data contention, thereb y simplifying system design. each access consists of four 36- bit data transfers in the case of CY7C2245KV18, in two clock cycles. these devices operate with a read latency of two cycles when doff pin is tied high. when doff pin is set low or connected to v ss then device behaves in qdr i mode with a read latency of one clock cycle. accesses for both ports are initiated on the positive input clo ck (k). all synchronous input and output timing are referenced fro m the rising edge of the input clocks (k and k ). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) outputs pass through output registers controlled by the rising edge of the input clocks (k and k ) as well. all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controll ed by the rising edge of the in put clocks (k and k ). CY7C2245KV18 is described in the following sections. read operations the CY7C2245KV18 is organized internally as four arrays of 256k 36. accesses are completed in a burst of four sequential 36-bit data words. read operations are initiated by asserting rps active at the rising edge of the positive input clock (k). the address presented to the address inputs is stored in the read address register. following the next two k clock rise, the corresponding lowest order 36-bit word of data is driven onto t he q [35:0] using k as the output timing reference. on the subsequent rising edge of k, the next 36-bit data word is drive n onto the q [35:0] . this process continues until all four 36-bit data words have been driven out onto q [35:0] . the requested data is valid 0.45 ns from the rising edge of the input clock (k or k ). to maintain the internal logic, each read access must be allowed t o complete. each read access consists of four 36-bit data words and takes two clock cycles t o complete. t herefore, read accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device ignores the sec ond read request. read accesses can be initiated on every other k clock rise. doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks (k and k ). when the read port is deselected, the CY7C2245KV18 first completes the pending read tran sactions. synchronous internal circuitry automatically tri-states the outputs following the ne xt rising edge of the negative input clock (k ). this enables for a seamless transition between device s without the insertion of wa it states in a depth expanded memory. doff input pll turn off ? active low . connecting this pin to ground turns off the pll inside the de vice. the timings in the pll turned off operation differs from those listed in th is data sheet. for normal operation, this pin can be connected to a pull up through a 10 k ? or less pull-up resistor. the device behaves in qdr i mode when the pll is turned off. in this mode, the device can b e operated at a frequency of up to 167 mhz with qdr i timing. tdo output tdo pin for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to a ny voltage level. nc /72m n/a not connected to the die . can be tied to a ny voltage level. nc /144m n/a not connected to the die . can be tied to a ny voltage level. nc /288m n/a not connected to the die . can be tied to a ny voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name i/o pin description
CY7C2245KV18 document number: 001-87885 rev. *d page 7 of 28 write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the following k clock rise the data presented to d [35:0] is latched and stored into the lower 36-bit write data register, provided bws [3:0] are asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [35:0] is also stored into the write data register, provided bws [3:0] are asserted active. this process continues for one more cycle until four 36 -bit words (a total of 144 bits) of data are stored in the sram. the 144 bits of data are then written into the memory array at the specified location. therefore, write accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device ignores the second write request. write accesses can be initiated on every other rising edge of the positive input clock (k). doing so pipelines the data flow such that 36 bits of data can be transferred into the device on ever y rising edge of the in put clocks (k and k ). when deselected, the write port ignores all inputs after the pending write operations are completed. byte write operations byte write operations are supported by the CY7C2245KV18. a write operation is initiated as described in the section write operations on page 7 . the bytes that are written are determined by bws 0 , bws 1 , bws 2 and bws 3 which are sampled with each set of 36-bit data words. asserting the appropriate byte write select input during the data portion of a write latches the dat a being presented and writes it into the device. deasserting the byte write select input during t he data portion of a write enab les the data stored in the device for that byte to remain unaltered . this feature can be used to simplify read, modify, or write ope ra- tions to a byte write operation. concurrent transactions the read and write ports on the CY7C2245KV18 operates completely independently of one another. as each port latches the address inputs on different clock edges, the user can read or write to any location, regardles s of the transaction on the oth er port. if the ports access the same location when a read follows a write in successive clock cycles, the sram delivers the most recent information associated with the specified address location. this includes forwardi ng data from a write cycle that was initiated on the previous k clock rise. read access and write access must be scheduled such that one transaction is initiated on any clock cycle. if both ports are selected on the same k clock rise, the arbitration depends on t he previous state of the sram. if both ports are deselected, the read port takes priority. if a read was initiated on the previo us cycle, the write port takes prior ity (as read operations can no t be initiated on consecutive cycles). if a write was initiated on t he previous cycle, the read port tak es priority (as write operatio ns can not be initiated on consecut ive cycles). therefore, asserti ng both port selects active from a deselected state results in alternating read or write opera tions being initiated, with the first access being a read. depth expansion the CY7C2245KV18 has a port select input for each port. this enables for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each p ort select input can deselect the s pecified port. deselecting a por t does not affect the other port. all pending transactions (read and write) are completed before the device is deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5 the value of the intended line impedance driven by the sram, the allowable range of rq to guarantee impedanc e matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq =1.5 v. the output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supp ly voltage and temperature. echo clocks echo clocks are provided on the q dr ii+ to simplify data captur e on high speed systems. two ec ho clocks are generated by the qdr ii+. cq is referenced with respect to k and cq is referenced with respect to k . these are free-running clocks and are synchronized to the input clock of the qdr ii+. the timing for the echo clocks is shown in the switching characteristics on page 22 . valid data indicator (qvld) qvld is provided on the qdr ii+ to simplify data capture on hig h speed systems. the qvld is gene rated by the qdr ii+ device along with data output. this sig nal is also edge-aligned with t he echo clock and follows the timing of any data pin. this signal is asserted half a cycle before valid data arrives. on-die termination (odt) these devices have an on-die termination feature for data input s (d [x:0] ), byte write selects (bws [x:0] ), and input clocks (k and k ). the termination resistors are in tegrated within the chip. the o dt range selection is enabled through ball r6 (odt pin). the odt termination tracks value of rq where rq is the resistor tied to the zq pin. odt range selection is made during power-up initialization. a low on this pin selects a low range that foll ows rq/3.33 for 175 ?? < rq < 350 ?? (where rq is the resistor tied to zq pin) ?? a high on this pin selects a high range that follows rq/1.66 for 175 ?? < rq < 250 ?? (where rq is the resistor tied to zq pin). when left floating, a high range termination value is selected by default. for a detailed description on the odt implementation, refer to the application note, on-die termination for qdrii+/ddrii+ srams . pll these chips use a pll that is designed to function between 120 mhz and the specified maximum clock frequency. during power-up, when the doff is tied high, the pll is locked after 20 ? s of stable clock. the pll can also be reset by slowing or stopping the input clocks k and k for a minimum of 30 ns. however, it is not necessary t o reset the pll to lock to the desired frequency. the pll automatically locks 20 ? s after a stable clock is presented. the pll may be disabled by applying ground to the doff pin. when the pll is turned off, the device behaves in qdr i mode (with one cycle latency and a longer access time). for information, refer to the application note, pll considerations in q drii/ddrii/q drii+/ddrii+ .
CY7C2245KV18 document number: 001-87885 rev. *d page 8 of 28 application example figure 2 shows two qdr ii+ us ed in an application. figure 2. application example (width expansion) d[x:0] arps wps bws kk q[x:0] zq sram#1 cq/cq d[x:0] arps wps bws kk q[x:0] zq sram#2 cq/cq data in[2x:0] data out [2x:0] address rps wps bws clkin1/clkin1 clkin2/clkin2 source k source k fpga / asic rq rq
CY7C2245KV18 document number: 001-87885 rev. *d page 9 of 28 truth table the truth table for CY7C2245KV18 follows. [4, 5, 6, 7, 8, 9] operation k rps wps dq dq dq dq write cycle: load address on the rising edge of k; input write data on two consecutive k and k rising edges. lCh h [10] l [11] d(a) at k(t + 1) ? d(a + 1) at k (t + 1) ? d(a + 2) at k(t + 2) ? d(a + 3) at k (t + 2) ? read cycle: (2.0 cycle latency) load address on the rising edge of k; wait two cycles; read data on two consec- utive k and k rising edges. lCh l [11] x q(a) at k (t + 2) ? q(a + 1) at k(t + 3) ? q(a + 2) at k (t + 3) ? q(a + 3) at k(t + 4) ? nop: no operation lCh h h d = x q = high z d = x q = high z d = x q = high z d = x q = high z standby: clock stopped stopped x x previous state previous state prev ious state previous state notes 4. x = don't care, h = logic high, l = logic low, ? represents rising edge. 5. device powers up deselected with the outputs in a tri-state c ondition. 6. a represents address location latched by the devices when t ransaction was initiated. a + 1, a + 2, and a + 3 represents th e address sequence in the burst. 7. t represents the cycle at whi ch a read/write operation is s tarted. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the t clock cycle. 8. data inputs are registered at k and k rising edges. data outputs are delivered on k and k rising edges as well. 9. ensure that when clock is stopped k = k = high. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 10. if this signal was low to ini tiate the previous cycle, this signal becomes a dont care for this operation. 11. this signal was high on previous k clock rise. initiating co nsecutive read or write operations on consecutive k clock rises is not permitted. the device ignores the second read or write request.
CY7C2245KV18 document number: 001-87885 rev. *d page 10 of 28 write cycle descriptions the write cycle description tab le for CY7C2245KV18 follows. [12, 13] bws 0 bws 1 bws 2 bws 3 k k comments l l l l lCh C during the data portion of a write sequence, all four b ytes (d [35:0] ) are written into the device. l l l l C lCh during the data portion of a write sequence, all four b ytes (d [35:0] ) are written into the device. l h h h lCh C during the data portion of a write sequence, only the l ower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h C lCh during the data portion of a write sequence, only the l ower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h lCh C during the data portion o f a write sequence, only the b yte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h C lCh during the data portion of a write sequence, only the b yte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h lCh C during the data portion o f a write sequence, only the b yte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h C lCh during the data portion of a write sequence, only the b yte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l lCh C during the data portion o f a write sequence, only the b yte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l C lCh during the data portion of a write sequence, only the b yte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h h lCh C no data is written into the device durin g this portion of a write operation. h h h h C lCh no data is written into the device durin g this portion of a write operation. notes 12. x = don't care, h = logic high, l = logic low, ? represents rising edge. 13. is based on a write cycle that was initiated in accordance w ith the truth table on page 9 . bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are ach ieved.
CY7C2245KV18 document number: 001-87885 rev. *d page 11 of 28 ieee 1149.1 serial boundary scan (jtag) this sram incorporates a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ie ee standard #1149.1-2001. the tap operates using jedec standard 1.8 v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull-up resistor. tdo must be left unconnected. upon power-up, the device comes up in a reset state, which does not interfere with the operation o f the device. test access port test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the regi sters and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information ab out loading the instruction register, see the tap controller state diagram on page 13 . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active , depending upon the current sta te of the tap state machine (see instruction codes on page 17 ). the output changes on the falling edge of tck. tdo is connected to the least significa nt bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is operating. at power-up, the tap is reset inter nally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram t est circuitry. only one regist er can be selected at a time through the instruction registers. da ta is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the fallin g edge of tck. instruction register three-bit instructions can be serially loaded into the instruct ion register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 14 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state, as de scribed in the previ ous section. when the tap controller is in the capture-ir state, the two lea st significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between td i and tdo pins. this enables shifting of data through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruct ion is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher densit y devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the input and output ring. the boundary scan order on page 18 shows the order in which the bits are connected. each bit corresponds to one of the bump s on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired int o the sram and can be shifted out when the tap controller is in the shift-dr state. the id regi ster has a vendor code and other information described in identification regist er definitions on page 17 . tap instruction set eight different instructions ar e possible with the three-bit instruction register. all co mbinations are listed in instruction codes on page 17 . three of these instructions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shif t-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction after it is shifted in, the tap controller must be moved into the update-ir state.
CY7C2245KV18 document number: 001-87885 rev. *d page 12 of 28 idcode the idcode instruction loads a v endor-specific, 32-bit code int o the instruction register. it also places the instruction regist er between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap controller is supplied a test-logic-reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is supplied during t he update ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instruct ions are loaded into the instruction register and the tap controller is in the capture-d r state, a snapshot of data on the input and output pins is captu red in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of m agnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, b ut there is no guarantee as to th e value that is captured. repeatable results may not be possible. to guarantee that the boundar y scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controllers capture setup plus hol d times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruct ion. if this is an issue, it is still possible to capture all other signals and simply ignore t he value of the ck and ck captured in the bounda ry scan register. after the data is captured, it is possible to shift out the dat a by putting the tap into the shift-dr state. this places the bounda ry scan register between t he tdi and tdo pins. preload places an initial data p attern at the latched parallel outputs of the boundary scan regi ster cells before the selectio n of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction regist er and the tap is placed in a shift -dr state, the b ypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are c onnected together on a board. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 m andates that the tap controller be able to put the output bus int o a tri-state mode. the boundary scan register has a special bit located at bit #10 8. when this scan cell, called the extest output bus tri-state, is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the outpu t (q-bus) pins, when the extest is entered as the current instruction. when high, it enab les the output buffers to drive the output bus. when low, this bi t places the output bus into a high z condition. this bit can be set by ent ering the sample/preload or extest command, and then shifting the desired bit into that cel l, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latches into the preload register . when the extest instruction is entered, this bit directly controls t he output q-bus pins. note that this bit is preset high to enable the output when the device is power ed up, and also when the tap controller is in the te st-logic-reset state. reserved these instructions are not imp lemented but are reserved for future use. do not use these instructions.
CY7C2245KV18 document number: 001-87885 rev. *d page 13 of 28 tap controller state diagram the state diagram for the tap controller follows. [14] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 14. the 0/1 next to each state represents the value at tms at th e rising edge of tck.
CY7C2245KV18 document number: 001-87885 rev. *d page 14 of 28 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 108 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical c haracteristics over the operating range parameter [15, 16, 17] description test conditions min max unit v oh1 output high voltage i oh = ?? 2.0 ma 1.4 C v v oh2 output high voltage i oh = ?? 100 ? a1.6Cv v ol1 output low voltage i ol = 2.0 ma C 0.4 v v ol2 output low voltage i ol = 100 ? aC0.2v v ih input high voltage 0.65 v dd v dd + 0.3 v v il input low voltag e C0.3 0.35 v dd v i x input and output load current gnd ? v i ? v dd C5 5 ? a notes 15. these characteristics pertain to the tap inputs (tms, tck, t di and tdo). parallel load levels are specified in the electrical characteristics on page 20 . 16. overshoot: v ih(ac) < v ddq + 0.35 v (pulse width less than t cyc /2), undershoot: v il(ac) > - 0.3 v (pulse width less than t cyc /2). 17. all voltage referenced to ground.
CY7C2245KV18 document number: 001-87885 rev. *d page 15 of 28 tap ac switching characteristics over the operating range parameter [18, 19] description min max unit t tcyc tck clock cycle time 50 C ns t tf tck clock frequency C 20 mhz t th tck clock high 20 C ns t tl tck clock low 20 C ns setup times t tmss tms set-up to tck clock rise 5 C ns t tdis tdi set-up to tck clock rise 5 C ns t cs capture set-up to tck rise 5 C ns hold times t tmsh tms hold after tck clock rise 5 C ns t tdih tdi hold after clock rise 5 C ns t ch capture hold after clock rise 5 C ns output times t tdov tck clock low to tdo valid C 10 ns t tdox tck clock low to tdo invalid 0 C ns notes 18. t cs and t ch refer to the set-up and hold time requirements of latching dat a from the boundary scan register. 19. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
CY7C2245KV18 document number: 001-87885 rev. *d page 16 of 28 tap timing and test conditions figure 3 shows the tap timing and test conditions. [20] figure 3. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo note 20. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
CY7C2245KV18 document number: 001-87885 rev. *d page 17 of 28 identification register definitions instruction field value description CY7C2245KV18 revision number (31:29 ) 000 version number. cypress device id (28:12) 11010010001100111 defines the type of s ram. cypress jedec id (11:1) 000001101 00 allows unique identification of sram vendor. id register presence (0) 1 indicates the presence of an id regist er. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 109 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and plac es the register between tdi and tdo. this operation does no t affect sram operation. sample z 010 captures the input and output contents. places the b oundary scan register between tdi and tdo. forces all sram output d rivers to a high z state. reserved 011 do not use: this instr uction is reserved for future use. sample/preload 100 captures the i nput and output ring contents. p laces the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instr uction is reserved for future use. reserved 110 do not use: this instr uction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this o peration does not affect sram operation.
CY7C2245KV18 document number: 001-87885 rev. *d page 18 of 28 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 06r 2810g 566a 841j 16p299g575b852j 2 6n 30 11f 58 5a 86 3k 3 7p 31 11g 59 4a 87 3j 47n 329f 605c 882k 5 7r 33 10f 61 4b 89 1k 6 8r 34 11e 62 3a 90 2l 7 8p 35 10e 63 2a 91 3l 8 9r 36 10d 64 1a 92 1m 9 11p 37 9e 65 2b 93 1l 10 10p 38 10c 66 3b 94 3n 11 10n 39 11d 67 1c 95 3m 12 9p 40 9c 68 1b 96 1n 13 10m 41 9d 69 3d 97 2m 14 11n 42 11b 70 3c 98 3p 15 9m 43 11c 71 1d 99 2n 16 9n 44 9b 72 2c 100 2p 17 11l 45 10b 73 3e 101 1p 18 11m 46 11a 74 2d 102 3r 19 9l 47 10a 75 2e 103 4r 20 10l 48 9a 76 1e 104 4p 21 11k 49 8b 77 2f 105 5p 22 10k 50 7c 78 3f 106 5n 23 9j 51 6c 79 1g 107 5r 24 9k 52 8a 80 1f 108 internal 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1h
CY7C2245KV18 document number: 001-87885 rev. *d page 19 of 28 power up sequence in qdr ii+ sram qdr ii+ srams must be powered up and initialized in a predefined manner to prevent undefined operations. power up sequence apply power and drive doff either high or low (all other inputs can be high or low). ? apply v dd before v ddq . ? apply v ddq before v ref or at the same time as v ref . ? drive doff high. provide stable doff (high), power and clock (k, k ) for 20 ? s to lock the pll. pll constraints pll uses k clock as its synchronizing input. the input must have low phase jitter, wh ich is specified as t kc var . the pll functions at fr equencies down to 120 mhz. if the input clock is unstable and the pll is enabled, then the pll may lock onto an incorrect frequency, causing unstable sram behavior. to avoid this, provide 20 ? s of stable clock to relock to the desired clock frequency. figure 4. power up waveforms > 20 s stable clock start normal operation doff stabl e (< +/- 0.1v dc per 50ns ) fix high (or tie to v ddq ) k k ddq dd v v / ddq dd v v / clock start ( clock starts after stable ) ddq dd v v / ~ ~ ~ ~ unstable clock
CY7C2245KV18 document number: 001-87885 rev. *d page 20 of 28 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user gui delines are not tested. storage temperature ........... .............. ....... C65 c to + 150 c ambient temperature with power applied ........... .............. .......... C55 c to +125 c supply voltage on v dd relative to gnd .... ...C0.5 v to +2.9 v supply voltage on v ddq relative to gnd ...... C0.5 v to +v dd dc applied to outputs in h igh z ........ C0.5 v to v ddq + 0.3 v dc input voltage [21] ........................... C0.5 v to v dd + 0.3 v current into outputs (low) .................................... .... 20 ma static discharge voltage (mil-std-883, m. 3015) ........................................ > 2,001 v latch-up current .............................................. ...... > 200 ma operating range range ambient temperature (t a ) v dd [22] v ddq [22] industrial C40 c to +85 c 1.8 0.1 v 1.4 v to v dd neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 197 216 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch-up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculation. for more details refer to a pplication note an 54908 accelerated neutron ser testing and calculation of te rrestrial failure rates electrical characteristics over the operating range dc electrical characteristics over the operating range parameter [23] description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage note 24 v ddq /2 C 0.12 C v ddq /2 + 0.12 v v ol output low voltage note 25 v ddq /2 C 0.12 C v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?? 0.1 ma, nominal impedance v ddq C 0.2 C v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss C 0.2 v v ih input high voltage v ref + 0.1 C v ddq + 0.15 v v il input low voltage C0.15 C v ref C 0.1 v i x input leakage current gnd ? v i ? v ddq C2 C 2 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled C2 C 2 ? a v ref input reference voltage [26] typical value = 0.75 v 0.68 0.75 0.95 v i dd [27] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 450 mhz ( 36) C C 1020 ma i sb1 automatic power-down current max v dd , both ports deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc , inputs static 450 mhz ( 36) C C 330 ma notes 21. overshoot: v ih(ac) < v ddq + 0.35 v (pulse width less than t cyc /2), undershoot: v il(ac) > - 0.3 v (pulse width less than t cyc /2). 22. power-up: assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 23. all voltage referenced to ground. 24. output are impedance controlled. i oh = ? (v ddq /2)/(rq/5) for values of 175 ? ? rq ? 350 ? . 25. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? ? rq ? 350 ? . 26. v ref(min) = 0.68 v or 0.46 v ddq , whichever is larger, v ref(max) = 0.95 v or 0.54 v ddq , whichever is smaller. 27. the operation current is calc ulated with 50% read cycle and 50% write cycle.
CY7C2245KV18 document number: 001-87885 rev. *d page 21 of 28 ac electrical characteristics over the operating range parameter [28] description test conditions min typ max unit v ih input high voltage v ref + 0.2 C v ddq + 0.24 v v il input low voltage C0.24 C v ref C 0.2 v capacitance parameter [29] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 1.8 v, v ddq = 1.5 v 4 pf c o output capacitance 4pf thermal resistance parameter [29] description test conditions 165-ball fbga package unit ? ja (0 m/s) thermal resistance (junction to ambient) socketed on a 170 220 2.35 m m, eight-layer printed circuit board 16.72 c/w ? ja (1 m/s) 15.67 c/w ? ja (3 m/s) 14.92 c/w ? jb thermal resistance (junction to board) 13.67 c/w ? jc thermal resistance (junction to case) 4.54 c/w ac test loads and waveforms figure 5. ac test loads and waveforms 1.25 v 0.25 v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75 v v ref = 0.75 v [30] 0.75 v under te s t 0.75 v device under te s t output 0.75 v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ? 28. overshoot: v ih(ac) < v ddq + 0.35 v (pulse width less than t cyc /2), undershoot: v il(ac) > - 0.3 v (pulse width less than t cyc /2). 29. tested initially and after any design or process change that may affect these parameters. 30. unless otherwise noted, tes t conditions are based on signal transition time of 2 v/ns, timing reference levels of 0.75 v, v ref = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the spe cified i ol /i oh and load capacitance shown in (a) of figure 5 .
CY7C2245KV18 document number: 001-87885 rev. *d page 22 of 28 switching characteristics over the operating range parameters [31, 32] description 450 mhz unit cypress parameter consortium parameter min max t power v dd (typical) to the first access [33] 1 C ms t cyc t khkh k clock cycle time 2.2 8.4 ns t kh t khkl input clock (k/k ) high 0.4 C ns t kl t klkh input clock (k/k ) low 0.4 C ns t khk h t khk h k clock rise to k clock rise (rising edge to rising edge) 0.94 C ns setup times t sa t avkh address set-up t o k clock rise 0.275 C ns t sc t ivkh control set-up to k clock rise (rps , wps ) 0.275 C ns t scddr t ivkh double data rate contro l set-up to clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.22 C ns t sd t dvkh d [x:0] set-up to clock (k/k ) rise 0.22 C ns hold times t ha t khax address hold after k clock rise 0.275 C ns t hc t khix control hold after k clock rise (rps , wps ) 0.275 C ns t hcddr t khix double data rate contro l hold after clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.22 C ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.22 C ns output times t co t chqv k/k clock rise to data valid C 0.45 ns t doh t chqx data output hold after output k/k clock rise (active to active) C0.45 C ns t ccqo t chcqv k/k clock rise to echo clock valid C 0.45 ns t cqoh t chcqx echo clock hold after k/k clock rise C0.45 C ns t cqd t cqhqv echo clock high to data valid C 0.15 ns t cqdoh t cqhqx echo clock high to data invalid C0.15 C ns t cqh t cqhcql output clock (cq/cq ) high [34] 0.85 C ns t cqhcq h t cqhcq h cq clock rise to cq clock rise (rising edge to rising edge) [34] 0.85 C ns t chz t chqz clock (k/k ) rise to high z (a ctive to high z) [35, 36] C 0.45 ns t clz t chqx1 clock (k/k ) rise to low z [35, 36] C0.45 C ns t qvld t cqhqvld echo clock high to qvld valid [37] C0.15 0.15 ns pll timing t kc var t kc var clock phase jitter C 0.15 ns t kc lock t kc lock pll lock time (k) 20 C ? s t kc reset t kc reset k static to pll reset [38] 30 C ns notes 31. unless otherwise noted, test conditions are based on signal transition time of 2 v/ns, timing reference levels of 0.75 v, v ref = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the spe cified i ol /i oh and load capacitance shown in (a) of figure 5 on page 21 . 32. when a part with a maximum frequency above 400 mhz is operat ing at a lower clock frequency, it requires the input timings o f the frequency range in which it is being operated and outputs data with the output timings of that frequ ency range. 33. this part has a voltage regulator internally; t power is the time that the power must be supplied above v dd minimum initially before a read or write operation can be initiated. 34. these parameters are extrapolated from the input timing para meters (t cyc /2 C 250 ps, where 250 ps is the internal jitter). these parame ters are only guaranteed by design and are not tested in production. 35. t chz , t clz , are specified with a load capacitance of 5 pf as in (b) of figure 5 on page 21 . transition is measured 100 mv from steady-state voltage. 36. at any given voltage and temperature t chz is less than t clz and t chz less than t co . 37. t qvld spec is applicable for both ri sing and falling edges of qvld si gnal.
CY7C2245KV18 document number: 001-87885 rev. *d page 23 of 28 switching waveforms read/write/deselect sequence figure 6. waveform for 2.0 cycle read latency [39, 40, 41] notes 38. hold to > v ih or < v il . 39. q00 refers to output from address a0. q01 refers to output f rom the next internal burst address following a0, that is, a0 + 1. 40. outputs are disabled (high z) one clock cycle after a nop. 41. in this example, if address a2 = a1, then data q20 = d10, q2 1 = d11, q22 = d12, and q23 = d13. write data is forwarded imme diately as read results. this note applies to the whole diagram.
CY7C2245KV18 document number: 001-87885 rev. *d page 24 of 28 ordering information the following table contains only the parts that are currently available. if you do not see what you are looking for, contact your local sales representative. for more information, visit the cypress w ebsite at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturers representativ es and distributors. to find t he office closest to you, visit us at http://www.cypress.com /go/datasheet/offices. ordering code definitions speed (mhz) ordering code package diagram package type operating range 450 CY7C2245KV18-450bzxi 51-85180 165-ball fbga (13 1 5 1.4 mm) pb-free industrial temperature range: i = industrial = C40 ? c to +85 ? c x = pb-free package type: bz = 165-ball fbga speed grade: 450 mhz v18 = 1.8 v v dd process technology: k = 65 nm part identifier technology code: c = cmos marketing code: 7 = sram company id: cy = cypress cy 2245 k - 450 bz x v18 i c 7
CY7C2245KV18 document number: 001-87885 rev. *d page 25 of 28 package diagram figure 7. 165-ball fbga (13 15 1.4 mm) bb165d/ bw165d (0.5 b all diameter) packag e outline, 51-85180 51-85180 *g
CY7C2245KV18 document number: 001-87885 rev. *d page 26 of 28 acronyms document conventions units of measure acronym description ddr double data rate eia electronic industries alliance fbga fine-pitch ball grid array hstl high-speed transceiver logic i/o input/output jedec joint electron devices engineering council jtag joint test action group lmbu logical multiple bit upset lsb least significant bit lsbu logical single bit upset msb most significant bit odt on-die termination pll phase locked loop qdr quad data rate sel single event latch-up sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select symbol unit of measure c degree celsius k ? kilohm mhz megahertz a microampere s microsecond ma milliampere mm millimeter ms millisecond mv millivolt ns nanosecond ? ohm pf picofarad % percent vvolt wwatt
CY7C2245KV18 document number: 001-87885 rev. *d page 27 of 28 document history page document title: CY7C2245KV18, 36-mbit qdr ? ii+ sram four-word burst architecture (2.0 cycle read latency) with odt document number: 001-87885 rev. ecn no. orig. of change submission date description of change ** 4024163 prit 09/03/2013 new data sheet. *a 4373800 prit 05/08/2014 updated application example : updated figure 2 . updated thermal resistance : updated values of ? ja parameter. included ? jb parameter and its details. *b 4571750 prit 11/18/2014 updated functional description : added for a complete list of related documentation, click here . at the end. *c 5374426 prit 07/26/2016 updated package diagram : spec 51-85180 C changed revision from *f to *g. updated to new template. completing sunset review. *d 6013959 rmes 01/04/2018 updated to new template. completing sunset review.
document number: 001-87885 rev. *d revised january 4, 2018 page 28 of 28 qdr rams and quad data rate rams comprise a new family of produ cts developed by cypress, idt, nec, renesas, and samsung. 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